a) Field of the Invention
The present invention relates generally to a silicon semiconductor device, and more particularly to a method of manufacturing a semiconductor device with silicide electrodes (interconnections).
b) Description of the Related Art
Fine elements and low power consumption circuits are required for semiconductor integrated circuits. In reducing power consumption, a CMOS (complementary metal-oxide-semiconductor) circuit is advantageous over other circuits. Fine MOS transistors lead to a problem of a short channel effect by which drain current uncontrollable by gate voltage flows under application of drain voltage. This short channel effect is likely to occur if source/drain regions are deep relative to the distance (channel length) thereof.
In order to suppress the short channel effect, shallow source/drain impurity diffusion regions are desired. A resistance of a shallow impurity diffusion region is high. It is effective to form a low resistance film on the surface of an impurity diffusion region in order to lower the resistance thereof. From this viewpoint, silicide formation technique is becoming important.
It is also desired to lower the resistance of a silicon electrode (interconnection) such as a gate electrode without increasing its thickness. To this end, silicide formation technique is also used. A silicon gate and source/drain regions of a transistor, particularly a MOS transistor, can be silicified by the same process.
FIGS. 5A to 5C, 6A to 6C, 8A, and 8B are diagrams explaining an example of the method of manufacturing MOS transistors by using a conventional self alignment type silicifying (salicifying) technique.
As shown in FIG. 5A, a buffer oxide film 137 and a silicon nitride (SiN.sub.x) film 138 are deposited on the surface of, for example, a p-type silicon substrate 121. A resist mask is then formed over the silicon nitride film 138 to pattern the film 138 in a predetermined shape. Thereafter, the resist mask is removed. The silicon nitride film 138 functions as an oxygen shielding film and as a mask at a thermal oxidation process.
As shown in FIG. 5B, the silicon substrate 121 is heated to a high temperature to expose it in an oxidizing atmosphere and form a thermal oxide film 122 on the surface of the silicon substrate 121 at the region not covered with the silicon nitride film 138. In this manner, the oxide film 122 is formed by local oxidation of silicon (LOCOS) at the region not masked by the silicon nitride film 138. Such an oxide film is commonly called a field oxide film.
As shown in FIG. 5C, after the LOCOS oxidation, the silicon nitride film 138 and the buffer oxide film 137 are removed and a gate oxide film 123 is formed to a thickness of, for example, about 10 nm by thermal oxidation or the like.
As shown in FIG. 6A, a polycrystalline silicon film 124 is deposited to a thickness of, for example, about 150 nm by CVD (chemical vapor deposition) over the gate oxide film 123 and field oxide film 122.
As shown in FIG. 6B, n-type impurity ions such as phosphorus (P) and arsenic (As) are implanted into the deposited polycrystalline silicon film 124.
If a p-channel MOS transistor is to be formed on an n-type silicon substrate, p-type impurity ions such as boron (B) are implanted. Instead of implanting impurity ions after the polycrystalline silicon film is formed, an impurity doped polycrystalline silicon film may be deposited. The ion implantation process illustrated in FIG. 6B may be omitted if the impurity concentration of the polycrystalline silicon film 124 becomes sufficiently high by an ion implantation process to be performed later.
As shown in FIG. 6C, a resist pattern is formed over the polycrystalline silicon film 124. By using this resist pattern as an etching mask, the polycrystalline silicon film 124 and gate oxide film 123 are selectively etched.
The gate electrode is etched by reactive ion etching (RIE) by an etchant gas of, for example, Cl.sub.2 +O.sub.2, or HBr. An insulating gate electrode structure of the gate oxide film 123 and polycrystalline silicon film 124 is therefore formed on the surface of the silicon substrate 121.
If an LDD (lightly doped drain) structure is to be formed, n-type impurity ions such as phosphorus and arsenic are lightly doped after the gate electrode structure is formed, to thereby form shallow n-type regions 126a and 127a. At this time, these n-type impurity ions are implanted also into the polycrystalline silicon film 124.
As shown in FIG. 7A, an silicon oxide film 125 is deposited to a thickness of, for example, about 200 nm by CVD.
As shown in FIG. 7B, the deposited silicon oxide film 125 is anisotropically etched by RIE using a mixed gas of CF.sub.4 +CHF.sub.3 as an etchant. RIE continues until the silicon oxide film 125 on the flat substrate surface is fully etched, leaving the silicon oxide film 125 only at the side walls of the gate electrode structure. In this manner, side walls 125 of the gate electrode are formed.
As shown in FIG. 7C, by using the gate electrode 124 with the side walls 125 as a mask, n-type impurity ions such as phosphorus and arsenic are implanted at a high concentration to form a source region 126 and a drain region 127.
As shown in FIG. 8A, a Ti film 128 is formed over the whole surface of the substrate 121 to a thickness of, for example, about 50 nm by sputtering or the like. The Ti film 128 contacts silicon on the source region 126, drain region 127, and polycrystalline silicon electrode 124, and is deposited on the silicon oxide at the other region.
As shown in FIG. 8B, a thermal treatment is performed, for example, at a temperature of about 700.degree. C., for about 30 seconds. This thermal treatment silicifies the Ti film 128 contacting silicon and forms a titanium silicide film 128a.
After the titan silicide film 128 is formed by a reaction between Ti and silicon, the substrate 121 is immersed in a mixed solution of aqueous ammonia and hydrogen peroxide to remove the unreacted Ti film 128. The silicidation reaction is further progressed by a thermal treatment at a temperature of 800.degree. C. for about 30 seconds. With the two thermal treatment processes, an TiSi.sub.2 film is formed on the surface of the polycrystalline silicide gate electrode 124, source region 126, and drain region 127.
Titanium silicide has several phases. The two thermal treatment processes efficiently form the TiS.sub.2 film.
A silicide film can thus be formed in a self-alignment manner only on the gate electrode and source/drain regions of a MOS transistor on the silicon surface surrounded by a field oxide film.
In connecting a conductive pattern formed over a semiconductor substrate to another conductive region by a wiring, the surface of the other conductive region is covered with an insulating film, a contact hole is formed in the insulation film, and a wiring pattern is formed for interconnecting the conductive pattern and other conductive region.
In the case of local interconnections for interconnecting a wire pattern formed on a field oxide film and a diffusion region on the substrate surface, if the processes of forming an interlevel insulation film and opening a contact hole can be omitted, it is very desirable in that semiconductor devices can be made small and the processes can be simplified.
U.S. Pat. No. 4,821,085 and U.S. Pat. No. 4,873,204 disclose the formation of such local interconnections. U.S. Pat. No. 4,821,085 discloses a technique of silicifying a Ti film contacting Si and deposited on a substrate with selectively exposed conductive regions, and at the same time, changing the surface of the Ti film into TiN, by heating the substrate in a nitrogen atmosphere. Nitriding the Ti film with a nitrogen gas progresses more preferentially on an oxide film than on Si. A wiring layer contacting the Ti silicide film on the Si surface can be formed. The TiN film is patterned thereafter to form local interconnections.
U.S. Pat. No. 4,873,204 discloses a technique of forming a refractory metal film on an Si substrate with partially exposed Si regions and forming a patterned amorphous Si film on the refractory metal film. A thermal treatment is thereafter performed to form Ti silicide only at the regions contacting the Si regions and amorphous Si pattern. A local interconnection is thus formed. With a local interconnection technique by silicifying, a wiring layer connected to the exposed silicon region can be formed in a self-alignment manner.
The manufacturing methods described above implant ions twice into the polycrystalline silicide gate electrode, even if an LDD structure is not formed. At the ion implanting process illustrated in FIG. 6B, different impurity ions are implanted into n- and p-channel MOS transistors. Therefore, different masks are required.
If the ion implanting process illustrated in FIG. 6B is omitted and impurities are implanted into the gate electrode only by the source/drain ion implanting process, the following problems arise.
The depth of source/drain regions becomes about 0.1 .mu.m (100 nm) or less as devices are scaled down and become progressively smaller. A polycrystalline silicon gate electrode is required to have a thickness of about 150 nm. If the source/drain regions and gate electrode are subjected to the same ion implantation and thermal treatment processes, the processes are insufficient for the polycrystalline silicon gate electrode, lowering its conductivity.
It is also difficult to convert the silicon surface doped with impurities at a high concentration into good metal silicide. Therefore, if the dose of ions implanted into the source/drain regions is too large, it becomes difficult to form a silicide film on the surface of the source/drain regions.
Although local interconnections using a silicide formation technique are very effective for making semiconductor devices smaller, it can be said that this technique is not still matured sufficiently.